Search - FPGA DDS

[Software Engineering] sji

Description: 频率合成技术在现代电子技术中具有重要的地位。在通信、雷达和导航等设备中，它可以作为干扰信号发生器；在测试设备中，可作为标准信号源，因此频率合成器被人们称为许多电子系统的“心脏”。直接数字频率合成（DDS——Digital Direct Frequency Synthesis）技术是一种全新的频率合成方法，是频率合成技术的一次革命。本文主要分析了DDS的基本原理及其输出频谱特点，并采用VHDL语言在FPGA上实现。对于DDS的输出频谱，一个较大的缺点是：输出杂散较大。针对这一缺点本文使用了两个方法加以解决。首先是压缩ROM查找表，-Abstract；The frequency synthesis technology has the important status in the modern electronic technology. In equipment such as correspondence, radar and navigation, it may work as the unwanted signal generator In the test facility, may work as the standard signal source, therefore the frequency synthesizer is called by the people as "the heart" of many electronic systems .DDS——Digital Direct Frequency Synthesis technology is one brand-new frequency synthetic method, is a frequency synthesis technology revolution. This paper analyzes the basic principle of DDS and its output frequency spectrum characteristic, and realizes it with VHDL language on FPGA. In regard to the output
Platform: | Size: 961536 | Author: 番薯军 | Hits:

[VHDL-FPGA-Verilog] Lab2a

Description: C Code for a Nios II to switch led on a board with an FPGA ALTERA
Platform: | Size: 1024 | Author: gios78 | Hits:

[Software Engineering] FPGA

Description: 针对MT9M111数字图像传感器,采用Cyclone系列 EP1C6Q240C6作为主控芯片,设计并实现了ITU-R BT.656视频数据的采集、色彩空间转换、DVI-I显示控制的数字视频转换系统。系统可以将传感器的输入图像以1280×960(60Hz)和 1280×1024(60Hz)格式输出到DVI-I显示器上,并具有图像静止功能,同时在系统空闲时,可以将系统设置为待机状态,来降低功耗。-Aimed at the digital image sensor MT9M111,used Cyclone EP1C6Q240C6 as the main control chip,designed and implemented the conversion system of the collection of the ITU-R BT.656 video data,color space conversion,and the display on DVI-I monitor.This system can display the image from the sensor on DVI-I monitor in the mode of 1280960(60 Hz)or 12801024(60 Hz),image freezing is also supported.Moreover,the system can be set into standby state when the system is idled,for low power consumption.
Platform: | Size: 563200 | Author: 将建 | Hits:

[SCM] ddsdds

Description: 摘要：介绍了直接数字频率合成 (DDS) 技术的基本原理，给出了基于Altera公司FPGA器件的一个三相正弦信号发生器的设计方案，同时给出了其软件程序和仿真结果。仿真结果表明：该方法生成的三相正弦信号具有对称性好、波形失真小、频率精度高等优点，且输出频率可调。关键词：直接数字频率合成；现场可编程门阵列；FPGA；三相正弦信号 (2009-01-04, VHDL, 99KB, 9次) -hgfhtht rrgtsrt rthg rgrswt sgethwrathwtHY TSRTTHSRHGWth rtyhthgrg rgsrg thrsrgsg rgsgrgthsrg
Platform: | Size: 568320 | Author: nbonwenli | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 基于DDS原理的几种信号发生器的设计的几篇论文，使用FPGA平台或者FPGA和PC共同平台实现-DDS-based signal generator several principles of design, the use of FPGA or FPGA platform and a common platform PC
Platform: | Size: 591872 | Author: 王霄洲 | Hits:

[VHDL-FPGA-Verilog] dds

Description: 如何利用FPGA产生DDS调频信号很具体的-How to make use of DDS generated FM signal FPGA specific
Platform: | Size: 756736 | Author: 梁梁 | Hits:

[VHDL-FPGA-Verilog] dds_easy

Description: 直接频率合成DDS模块的ise工程，可以直接下载，在Spartan3/Spartan3E上验证通过。该DDS模块可以产生双通道的不同频率的正弦波，也可以产生同频的任意相位差的相移波形。本模块累加器位数为32位，可以产生12位相位精度12位量化精度的正弦波。该设计例化一个Block Ram，为节省储存空间仅需要储存1/4周期的数据。根据需要，可以重新修改数据，改变波形。-DDS direct frequency synthesizer module ，ise project, can be directly downloaded through the Spartan3/Spartan3E and tested successfully. The DDS module can generate two-channel sine wave of different frequency, or produce the same frequency arbitrary waveform phase difference of the phase shift. There is a 32-bit accumulator to generate 12 bit phase-precision 12-bit quantization precision of the sine wave. Cases the design of a Block Ram, in order to save storage space need to store only 1/4 cycle of data. Necessary, can modify data, change the waveform.
Platform: | Size: 471040 | Author: 郭先生 | Hits:

[VHDL-FPGA-Verilog] dds

Description: 基于fpga的函数发生器设计通过fpga实现正弦波输出-基于fpga的函数发生器
Platform: | Size: 62464 | Author: 江孝栋 | Hits:

[VHDL-FPGA-Verilog] FPGADDS

Description: dds，FPGA波形发生器,波表，接受，发送-dds, FPGA waveform generator, wave form, to receive, send
Platform: | Size: 540672 | Author: 伟贤 | Hits:

[VHDL-FPGA-Verilog] dds

Description: dds 驱动 ad9851 fpga vhdl-ad9851 dds ad9851 fpga vhdl
Platform: | Size: 1544192 | Author: ZHANGLONG | Hits:

[SCM] DDS

Description: 基于FPGA的DDS程序，可产生任意频率任意相位的波形-FPGA-based DDS program, can generate any frequency arbitrary waveform phase
Platform: | Size: 2971648 | Author: juan | Hits:

[SCM] dds

Description: 基于单片机与FPGA的DDS程序代码，产生任意波形-DDS-based MCU with FPGA-code, resulting in arbitrary waveform
Platform: | Size: 345088 | Author: jiangjun | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 本代码可以用于产生正余弦信号波形，利用FPGA内部的ROM放置一个正余弦采样点的数据表格，通过循环取址的方法，实现波形连续输出。-This code can be used to generate positive cosine signal waveforms, using FPGA' s internal ROM to place a sampling point is the cosine of the data tables, the circulation method of taking the site to achieve a continuous output waveform.
Platform: | Size: 484352 | Author: 蔡野锋 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 同时用verilog 语言编写dds原代码用于生成正余弦波，并在FPGA平台进行验证-described dds direct digital frequency synthesis of the basic tenets addition to the use of verilog prepared dds source used to produce sine, and FPGA development platform for verification
Platform: | Size: 1024 | Author: scond | Hits:

[VHDL-FPGA-Verilog] 51-DDS

Description: 不仅包含FPGA源码还包含51单片机控制源码，已经实现DDS功能，绝对原创。-Includes not only the FPGA source code also includes a 51 SCM control source, has been achieved DDS functions, absolutely original.
Platform: | Size: 2185216 | Author: 张文琪 | Hits:

[VHDL-FPGA-Verilog] dds

Description: 基于FPGA的直接数字频率合成器（DDS）的设计-FPGA-based direct digital frequency synthesizer (DDS) design of
Platform: | Size: 1024 | Author: sunshine | Hits:

[Other] DDS

Description: 这个一个基于FPGA的DDS原代码可以生成正弦和余弦两种波形-This is a DDS code bepend on FPGA ,it can generate two waves.
Platform: | Size: 9216 | Author: wuyanjun | Hits:

[VHDL-FPGA-Verilog] dds

Description: dds信号发生器，硬件测试过，效果良好。文件包含整个fpga开发过程产生的所有文件-dds signal generator, the hardware tested to good effect. File contains the entire fpga development process of all documents generated
Platform: | Size: 232448 | Author: wdw | Hits:

[Other] DDSFPGA_cylone

Description: DDS FPGA 模块，实用，欢迎大家下载-DDS FPGA programmer
Platform: | Size: 637952 | Author: 吴小平 | Hits:

[Other] DDS

Description: dds双通道波形发生器调制解调 fpga-dds sin cos phase
Platform: | Size: 580608 | Author: 春天 | Hits:

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[Software Engineering] sji

[VHDL-FPGA-Verilog] Lab2a

[Software Engineering] FPGA

[SCM] ddsdds

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] dds

[VHDL-FPGA-Verilog] dds_easy

[VHDL-FPGA-Verilog] dds

[VHDL-FPGA-Verilog] FPGADDS

[VHDL-FPGA-Verilog] dds

[SCM] DDS

[SCM] dds

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] 51-DDS

[VHDL-FPGA-Verilog] dds

[Other] DDS

[VHDL-FPGA-Verilog] dds

[Other] DDSFPGA_cylone

[Other] DDS

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